Short Courses

Over the past two decades significant progress has been made using spins in semiconductors as qubits for quantum computing, yet semiconductor qubits currently trail other architectures (including those utilizing superconductors or trapped ions) in number of demonstrated qubits. No architecture has yet achieved the number of qubits needed to reach the promise of quantum computing, and semiconducting qubits’ potential lies in the ability to scale more rapidly, both in terms of quantum-coherent control and fabrication. In this tutorial, we review gate-defined semiconductor spin qubits and discuss fabrication concerns that are unique to the technology, as well as those common with CMOS integrated circuits. We consider the demands for spin qubits applied to device and process design and process control. We review the fabrication and operation of major types of spin qubits, including donor spin qubits, single-spin “Loss-DiVincenzo” qubits, and triple-spin exchange-only qubits. We then discuss the challenges of quantum fabrication in low-volume, high-mix fabrication environment focused on research and development using electron-beam lithography.  We next discuss device failure mechanisms at quantum-relevant temperatures (typically ~0.1 K) such as poor gate connectivity, poor signal delivery, electrostatic disorder (similar to threshold uniformity), charge noise, magnetic noise, and accessibility of excited quantum states. Finally, we discuss HRL’s approach to reliable quantum technology: the SLEDGE (single-layer etch-defined gate electrode) platform.