Qiangfei Xia

University of Massachusetts, Amherst

Emerging Memory-Centric AI Hardware: Materials, Integration, and System on a Chip

Artificial intelligence (AI) has become ubiquitous in daily life; however, most recent breakthroughs have been driven primarily by advances in algorithms and software, while progress in underlying hardware has lagged behind. To sustain continued growth in computing performance and energy efficiency, intensive efforts are underway to move the hardware beyond Moore’s Law by exploring new materials, devices, technologies, and computing paradigms. In particular, emerging devices leveraging physical mechanisms such as spin, phase transitions, and ionic charge transport, together with computing paradigms like in-memory computing, are attracting significant attention as promising platforms for next-generation, high-efficiency AI hardware.

This short course highlights the critical role of materials and integration in enabling emerging memory-centric AI hardware, bridging device-level physics with system-level requirements for analog in-memory computing in artificial neural networks. The course begins with an overview of key memory technologies actively pursued for AI computing, including SRAM, FLASH, phase-change memory, magnetoresistive random-access memory (MRAM), resistive random-access memory (RRAM), and ferroelectric memory. Building on this foundation, the course focuses on non-volatile memristive devices, which encode analog information through distinct resistance states enabled by ionic motion and defect dynamics. When organized into crossbar arrays, these devices naturally support massively parallel multiply–accumulate operations, leveraging physical laws to deliver high computational throughput and energy efficiency.

The course then addresses key challenges and practical solutions for integrating memristive devices into large-scale arrays, outlining a clear path from early, experimental fabrication to reliable, high-volume manufacturing of AI hardware accelerators. In particular, we will present a memristive system-on-a-chip (SoC) that integrates memristive crossbar arrays with CMOS technology on a single chip, highlighting our recent lab-to-fab transfer initiative supported by the CHIPS Act. Finally, the course will showcase the use of memristive SoCs across a range of edge-intelligence applications, including neural networks and signal processing.

About Qiangfei Xia

Dr. Xia is the Dev and Linda Gupta Professor of Electrical and Computer Engineering at UMass Amherst and head of the Nanodevices and Integrated Systems Lab (http://nano.ecs.umass.edu). Before joining UMass, he spent three years at Hewlett-Packard Laboratories, where he demonstrated the first memristor/CMOS hybrid chip. He received his Ph.D. in Electrical Engineering in 2007 from Princeton University. Dr. Xia’s current research interests include beyond-CMOS devices, enabling fabrication technologies, and integrated systems with applications in machine intelligence, reconfigurable RF systems, and hardware security. He has received a DARPA Young Faculty Award, an NSF CAREER award, the Barbara H. and Joseph I. Goldstein Outstanding Junior Faculty Award, an Outstanding Senior Faculty Award, and the Chancellor’s Medal (the highest recognition bestowed upon faculty by UMass Amherst). He is a Highly Cited Researcher, recognized by Clarivate for four consecutive years to date, and an elected IEEE Fellow “for contributions to resistive memory arrays and devices for in-memory computing.”